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Published 20 hours ago • verified publisher icon romulus0914

open-source simulation

Open jinz2014 opened this issue 7 years ago • 1 comments

HI Romulus,

Can you please update your Makefile for the system simulation using Verilator ? It seems that only ncverilog is supported.

Thanks for your reply.

jinz2014 avatar Nov 18 '18 14:11 jinz2014

HI Romulus,

Can you please update your Makefile for the system simulation using Verilator ? It seems that only ncverilog is supported.

Thanks for your reply.

/Hi Jinz2014,

Did you find the solution? Because I am currently doing a project and stuck at the same problem as u mention above. Could you give me some advice or idea how to solve? Because I use Quartus ll Prime to run the Verilog file and it has a lot errors.

Look forward your reply. Thanks

ming114 avatar May 14 '20 19:05 ming114