Rodrigo A. Melo

Hi. I don't know if you fixed your problem, but it seems related to your python installation. If you need help ask again in your current state and I can...

Hi @andreaskuster Only to clarify, I am simply a recent user of cocotbext-axi. I can't right now, but I will try to reproduce it and let you know. Let me...

Ok, I didn't know about the cocotb limitation using Verilator. I generally use cocotb with GHDL or iverilog.

Hi @alexforencich this issue was already solved, and the problem (missing cocotb-test) is already involved in another issue (#10), so it can be closed.

Got it, I'm going to try with the AXI/AXIL RAM and let you know.

I successfully used AxiLiteRAM with my AXI4 Lite master (and I fixed some issues as consequence). Great idea to easily check the basic functionality of a master ;-) I have...

I am using AxiLiteRAM: ``` axil_ram = AxiLiteRam(AxiLiteBus.from_entity(dut), dut.aclk) ``` And here is the exception: ``` 32.00ns INFO The core was reset 36.00ns ERROR Exception raised by this forked coroutine...

Yes, it works with the current version at master :-D Based on one of the last logs (Fix AxiLiteSlave wrapper), I re-check `axil_slv = AxiLiteSlave(AxiLiteBus.from_entity(dut), dut.aclk)` and it also works,...

I see. What you say is something to also solve #20. Could be great. In the meantime... Any hack/workaround to convert the signal names of the instantiated dut in lower...

Probably the same as #26