Robert Szczepański
Robert Szczepański
This introduces PLL into HPS design with an additional option to enable/disable output clocks. It makes power consumption much higher. Initial tests with multimeter result in 70mW when CFU is...
Hi, there is an issue with updating RapidWright in [chipsalliance/fpga-tool-perf](https://github.com/chipsalliance/fpga-tool-perf) repository. I was able to bisect this issue to 3042468 commit which reverts some stuff, does it require any adjustments...
This PR allows to run tests for LIFCL-17 and LIFCL-40 with `nextpnr-fpga-interchange` toolchain. Right now tests fail due to lack of proper support on Yosys/Nextpnr part.
This PR applies a filelist patch for BlackParrot core in order to make it synthesizable in Synlig, the patch is the same as the one used in [synlig](https://github.com/chipsalliance/synlig/blob/main/tests/black_parrot/black_parrot_patches/0001_use_synth_filelist.patch). Even though...
There is a new VeeR config parameter `jtag_type` that accepts values `cltapc` (centralized TAP controller) and `emtapc` (Embedded TAP controller). The first one supports IDCODE TAP command, the latter does...
This PR introduces logic updates for both QL_DSP2 and QL_DSP3 modules. FYI @tpagarani.
This PR is a solution to #60. It doesn't affect current CI workflow steps but there are few additional steps. After successfully building vanilla repository examples, CI patches them so...
This PR addresses issues reported in [caliptra-sw#1220](https://github.com/chipsalliance/caliptra-sw/issues/1220) and [VeeR-EL2#88](https://github.com/chipsalliance/Cores-VeeR-EL2/issues/88). The `TEC_RV_ICG` module used in `rvdffpcie` operates on different logic for Verilator, `enable` signal is only sampled on negative clock edge....
Test for issue https://github.com/chipsalliance/caliptra-rtl/issues/523 resolved by PR https://github.com/chipsalliance/caliptra-rtl/pull/541. The test flow description: 1. Initiate Caliptra boot flow from the testbench typical for every test suite. The test suite awaits `BOOTFSM_GO`...