Robert Szczepański

[netlists.zip](https://github.com/Xilinx/RapidWright/files/9672277/netlists.zip) Sure, I generated these with: ``` python3 exhaust.py --project vexriscv --toolchain nextpnr-fpga-interchange --board arty-a100t --build_type vexriscv-nextpnr-fpga-interchange-arty-a100t --fail --timeout 7200 ```

Thanks @eddieh-xlnx, I just had a chance to test this on hardware and I can confirm that with your fix I am able to build working bitstream.

Hi @algrobman, it looks like the error you've attached occurs when you try to build VeeR core without having all required submodules. Please make sure that command `git submodule update...

Hi, the following error you've encountered: ``` /user/ajay.silla/RISCV_TOOL/riscv/bin/../lib/gcc/riscv64-unknown-elf/12.1.0/../../../../riscv64-unknown-elf/bin/ld: /lib64/libc.so.6: version `GLIBC_2.27' not found (required by /user/ajay.silla/RISCV_TOOL/riscv/bin/../lib/gcc/riscv64-unknown-elf/12.1.0/../../../../riscv64-unknown-elf/bin/ld) collect2: error: ld returned 1 exit status ``` is related to the version of...

@googlebot I fixed it.