Minor defect in ghrd_top.v

[affe00]

Hello,

In CycloneVSoC-examples/FPGA-hardware/DE1-SoC/FPGA_DMA/ghrd_top.v, line 335:

.axi_signals_aruser (pio_controlled_axi_signals[ARPROT_BASE+: ARPROT_SIZE]), .axi_signals_arprot (pio_controlled_axi_signals[ARUSER_BASE+: ARUSER_SIZE])

The name of inputs and the parameter macros seems to be reversed.

This might not be a problem now, when you use them, it may be hard to understand.

Best Regards, affe00

[robertofem]

Hi,

thank you for mentioning the problem. Yes they are reversed. It is strange. They have different width and the compiler did not complain. Anyway I dont think these signals affect the performance. AXCACHE are the ones really important. I will add this as an issue into the repo to fix it when i have moretime. If you fix it and you want to do a pull request it is also welcomed.

Best regards, roberbot

El mar., 11 dic. 2018 a las 16:00, affe00 ([email protected]) escribió:

Hello,

In CycloneVSoC-examples/FPGA-hardware/DE1-SoC/FPGA_DMA/ghrd_top.v, line 335:

.axi_signals_aruser (pio_controlled_axi_signals[ARPROT_BASE+: ARPROT_SIZE]), .axi_signals_arprot (pio_controlled_axi_signals[ARUSER_BASE+: ARUSER_SIZE])

The name of inputs and the parameter macros seems to be reversed.

This might not be a problem now, when you use them, it may be hard to understand.

Best Regards, affe00

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[ranshalit]

Hi, Is it fixed in git ? what should be the fix ? Thanks

[robertofem]

No. It is not fixed in git yet, otherwise I would have closed the issue. What should be changed is that ARPROT macros are asigned to aruser signals and viceversa. You have to switch the content inside the parenthesis in these 2 lines. You can do it and do a pull request if you wish