PPC: Add `cache_line_block_size` configs to PPC plugin

[Rot127]

Is your feature request related to a problem? Please describe.

The dcbz instruction zeros a cache line block and the memory it belongs to. The size of this block depends on the CPU. Sometimes it is 32, 64 or 128 bytes. (Check out the qemu settings for each CPU.) Currently this value is hardcoded in RZIL (128) and ESIL (32) but it shouldn't.

Describe the solution you'd like

A plugin config should be added which allows to set the cache line size manually. plugin.ppc.dcache_line_size and plugin.ppc.icache_line_size.

Describe alternatives you've considered

Alternatively all kind of CPUs can be added and the setting could be set depending on analysis.cpu. Or both.

Additional context

RZIL dcbz implementation: https://github.com/Rot127/rizin/blob/0b8c56c5764c586139b192b846346de1d86eedee/librz/analysis/arch/ppc/ppc_il_ops.c#L228-L229 QEMU cpu_init.c with cahce line size values: https://github.com/quic/qemu/blob/c55e3370c359713ff1e2a3392f36978c629c20c8/target/ppc/cpu_init.c Example of plugin configs: https://github.com/rizinorg/rizin/blob/4abd2028da7d8d5e4fab0002bc5080896fa2c3e6/librz/asm/p/asm_hexagon.c#L139-L179