rizin
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rizinorg
UNIX-like reverse engineering framework and command-line toolset.
**Your checklist for this pull request** - [x] I've read the [guidelines for contributing](https://github.com/rizinorg/rizin/blob/master/DEVELOPERS.md) to this repository - [x] I made sure to follow the project's [coding style](https://github.com/rizinorg/rizin/blob/master/DEVELOPERS.md#code-style) - [x]...
My environment: ArchLinux, x86_64, GCC 12.1.1 20220730 1. Get https://github.com/rizinorg/rizin/releases/download/v0.4.0/rizin-src-v0.4.0.tar.xz 2. Unpack it, and cd into rizin-v0.4.0 3. Get test/bins: make -C test/bins (I got 7d0c31ac7711de9c4d37f5047200dc5a407ff713) 4. Run: meson -Duse_sys_libzip=enabled...
Currently, both modes are implemented completely independently, sometimes with code duplication/copy-paste. I propose to reduce the code and feature duplication by: 1. Migrate **Visual** mode from commands to the API:...
# capstone-3 ``` FAILED: librz/analysis/librz_analysis.so.0.5.0.p/arch_ppc_ppc_il.c.o gcc -Ilibrz/analysis/librz_analysis.so.0.5.0.p -I. -I.. -Ilibrz -I../librz -Ilibrz/include -I../librz/include -I../librz/analysis/arch/gb -Ilibrz/util/sdb/src -I../librz/util/sdb/src -Ilibrz/util/sdb -I../librz/util/sdb -I../librz/asm/arch/include -I../librz/asm/arch -I../librz/asm/arch/h8300 -I../librz/asm/arch/hexagon -I../librz/asm/arch/msp430 -I../librz/asm/arch/rsp -I../librz/asm/arch/mcore -I../librz/asm/arch/v850 -I../librz/asm/arch/propeller -I../librz/asm/arch/ebc -I../librz/asm/arch/cr16 -I../librz/asm/arch/8051...
**Is your feature request related to a problem? Please describe.** The ISA v3 only `ca32` and `ov32` flags and register `ppr32` are not implemented. While this is not a huge...
# First stage (DONE) ## High-priority - [x] `librz/analysis/p/analysis_avr.c` https://github.com/rizinorg/rizin/pull/1890 - [x] `librz/analysis/p/analysis_arm_cs.c` ARMv7 https://github.com/rizinorg/rizin/pull/2241 - [x] `librz/analysis/p/analysis_arm_cs.c` ARMv8 https://github.com/rizinorg/rizin/pull/2354 - [x] `librz/analysis/p/analysis_ppc_cs.c` https://github.com/rizinorg/rizin/pull/2823 - [x] `librz/analysis/p/analysis_x86_cs.c` https://github.com/rizinorg/rizin/pull/2747 https://github.com/rizinorg/rizin/pull/3865 -...
**Is your feature request related to a problem? Please describe.** The PPC RZIL code doesn't implement exception handling although there is a least the `MTSPR`/`MFSPR` and `INVALID` instruction which could...
**Your checklist for this pull request** - [x] I've read the [guidelines for contributing](https://github.com/rizinorg/rizin/blob/master/DEVELOPERS.md) to this repository - [x] I made sure to follow the project's [coding style](https://github.com/rizinorg/rizin/blob/master/DEVELOPERS.md#code-style) - [...
Many tests when using on capstone-next are broken. ``` [XX] /home/deroad/rizin/test/db/analysis/x86_64 a8 analyze bytes RZ_NOPLUGINS=1 /home/deroad/rizin/build-capnext/binrz/rizin/rizin -escr.utf8=0 -escr.color=0 -escr.interactive=0 -N -Qc 'e asm.arch=x86 e asm.bits=64 e asm.os=linux a8 55| '...
**Is your feature request related to a problem? Please describe.** While Rizin supports the VLE extension via the internal `libvle` the instructions are not uplifted to RZIL yet. One challenge...