Idea: add which cores are possible to put on an ASIC, and which ones are FPGA-oriented

[mgielda]

This is not trivial to implement for the plethora of cores already on the list, but a good suggestion.

[stnolting]

Good idea! I would add another "generic" category and define some points how to categorize a certain core:

• FPGA: Core maybe uses FPGA-specific primitives/macros/attributes; scripts for certain synthesis flows; example top entity for certain FPGA dev board; ...
• ASIC: Core maybe uses stuff that is not very common / bad practice on FPGAs like clock gating or latches; ...
• Generic: Plain VHDL/Verilog/SystemC/you-name-it; no primitives/macros/attributes/etc. at all; technology-independent

[AESASH]

I second that

[stnolting]

I have just studied the new RISC-V compliance test framework v2 for porting it. Now that the new version has been officially released, how about adding a new column/category "RISC-V compliance" to show which tests (like rv32i_m/I, rv32i_m/M, ...) of the compliance framework a certain core passes? 🤔