Possible reachable assertion when updating PTEs

[Timmmm]

The virtual memory code has an assertion "invalid physical address in TLB" that happens when you have a TLB hit, and the PTE A/D bits need to be updated, and the write fails (e.g. due to PMA/PMP).

I don't think that's correct, because that path is easily reachable. Just map a page, access it so it's in the TLB, then set up PMP so that the PTE is inaccessible, and the write to the page.

I am working on a unit test for this to demonstrate it, and a fix.