Implement format-specific encoding mechanism

[ThinkOpenly]

This is a draft, with some extraneous commits included that greatly facilitate testing. The only important commit is marked "[DRAFT]", and reviews should be confined to that.

There's still a lot of content, so if I may direct the reviewers eyes:

• model/riscv_insts_begin.sail: This sets up the new global data content. In particular:
  • union instruction_input: A tagged union for all of the inputs for each instruction format.
  • scattered mapping fmtencdec: A new mapping from ast to instruction_input. Intended to replace scattered mapping encdec.
  • enum Format: one enum value per format.
  • scattered function opcode2format: maps 7-bit opcode values to the associated format enum.
• `model/riscv_insts_end.sail:
  • mapping fmt2bits: A new mapping from instruction_input to the 32-bit opcode value. This contains one bidirectional mapping for each format. This is a central location for enforcing opcode layouts, including field order and width, as well as important things like clipping low-order bits of field values where those bits have presumed/enforced values.
• model/riscv_insts_base.sail, model/riscv_insts_next.sail, model/riscv_insts_zicsr.sail:
  • Examples of use of opcode2format to explicitly bind an instruction to its respective format.
  • Examples of use of fmtencdec: to map ast inputs and constant values to the appropriate instruction_input tagged union member.
  • Note here that the encdec (renamed oldencdec) is obsoleted, and can be ignored, but I left it in for comparison/review purposes.