sail-riscv
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Add support for HPM counters
Implements Hardware Performance Monitoring counters, but only by making the registers available. Their values only change if explicitly written to and all values are legal.
All 32 HPM counters are always implemented (the spec says this "should" be the case), and a platform callback sys_writable_hpm_counters is added to allow making any of them read-only. I haven't hooked sys_writable_hpm_counters up to CLI flags because Codasip does not use the CLI flags and it is quite tedious, and hopefully going to change when riscv-config is used.
Finally this adds menvcfg and senvcfg to the CSR name map which I forgot to do previously.
Test Results
396 tests ±0 396 :white_check_mark: ±0 0s :stopwatch: ±0s 4 suites ±0 0 :zzz: ±0 1 files ±0 0 :x: ±0
Results for commit 01b63cd6. ± Comparison against base commit fd1be4b5.
:recycle: This comment has been updated with latest results.
"High Performance Counters" should be "Hardware Performance Counters"?
Also do we need to guard these with a (always-true)
haveZihpm()function?
Good call, I'll add that too.
@billmcspadden-riscv I think it's ok if you double check this since you've also done a lot of HPM stuff.
@billmcspadden-riscv I've rebased this.
@billmcspadden-riscv please can you merge this? It's ready to go.