sail-riscv
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riscv
riscv_sim.cpp: add SIGINT processor.
What's the motivation here? Adding explicit signal handlers is usually something that should be avoided if at all possible.
Test Results
2 101 tests ±0 2 101 ✅ ±0 18m 1s ⏱️ +3s 1 suites ±0 0 💤 ±0 1 files ±0 0 ❌ ±0
Results for commit fdec1ae1. ± Comparison against base commit 87eb6fb8.
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What's the motivation here? Adding explicit signal handlers is usually something that should be avoided if at all possible.
to generate the show execution times on ctrl-c.
[ariel@archlinux sail-riscv]$ build/c_emulator/sail_riscv_sim os-boot/linux/fw_payload.elf --no-trace -p --device-tree-blob os-boot/linux/build/sail.dtb -l 1000000000
will show execution times on completion.
using os-boot/linux/build/sail.dtb as DTB file.
Read 1655 bytes of DTB from os-boot/linux/build/sail.dtb.
Running file os-boot/linux/fw_payload.elf.
ELF Entry @ 0x80000000
HTIF located at 0x80042a78
^CInitialization: 144 msecs
Execution: 1909 msecs
Instructions: 116907
Perf: 61.240 Kips
Yeah we should avoid touching signal handlers at all costs. They're extremely error prone (see Alex's comment for example) and this doesn't seem like a big enough benefit.