riscv-plic-spec
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Reserved address access behavior undefined
What's the expected behaviour of reserved addresses? WARZ, return SLVERR, something else, or implementation defined?
In the RISC-V world "reserved" usually means anything can happen, basically the same as C's Undefined Behaviour.
It's not spelled out anywhere very explicitly unfortunately and it isn't actually universal.
The unprivileged spec has a section on UNSPECIFIED behaviour (anything can happen) and then in some cases it explicitly maps "reserved" to "UNSPECIFIED" e.g.
The behavior upon decoding a reserved instruction is UNSPECIFIED.
But in most cases it just says "reserved" and then who knows. I suppose it is literally unspecified... because the specification doesn't say.
In some cases reserved does have some constraints though, e.g. for the fence instruction:
The unused fields in the FENCE.I instruction, funct12, rs1, and rd, are reserved for finer-grain fences in future extensions. For forward compatibility, base implementations shall ignore these fields, and standard software shall zero these fields.