riscv-opcodes
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riscv
RISC-V Opcodes
1. Add dcsr.debugver, dcsr.ebreakvs, dcsr.ebreakvu, dcsr.stepie, dcsr.stopcount, dcsr.v, dcsr.mprven, and dcsr.nmip definitions. 2. Mark dcsr.xdebugver, dcsr.ndreset, dcsr.fullreset, dcsr.ebreakh, dcsr.stopcycle, dcsr.debugint, and dcsr.halt deprecated. Those field definition are kept for backward...
It seems that the information about the position and range of the arguments is not encoded, and this information is clearly described in the specification. If a downstream program is...
The version of encoding.h is not even cloe to up-to-date. It doesn't even have all the CSRs in the ratified priv spec (e.g. PMPCFGx, PMPADDRx). This needs to be regenerated...
While the individual code generators are useful, it'd be nice to have a machine-readable version-- sometimes the default generators just aren't a fit! `instr_dict.yaml` almost gets there, but it only...
Hello, For the standard/regular instructions, I think checking for encoding conflict is necessary. Note that only checking encoding conflict for instructions that belong to the same base extension. For example,...
The spec for zc extension(version 0.70.3) can be found in [zc spec](https://github.com/riscv/riscv-code-size-reduction/releases/tag/v0.70.3-TOOLCHAIN_DEV)
This may be debatable: the base `opcodes` table does a reasonable job a naming the individual fields, suchs as `rs1`, `imm12`, `bimm12lo`, `jimm20`, etc. Enough that you can make a...
According to: https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#116-vector-single-width-shift-instructions But in https://github.com/riscv/riscv-opcodes/blob/master/opcodes-rvv "simm5" is used. I think it should be "zimm5" instead.
The parser uses things like masks and matches. From the parsers code, I infer that masks and matches are used for determining what instruction is being (de)coded. I'm writing a...
