When the ss instruction accesses a page table entry with xwr=3b001 and the memory attribute is non-idempotent, should it report a store/AMO access-fault fault or a store/AMO page-fault ？

[chara811]

[kacouane]

Hello, for the priority of errors, you should refer to the privilege spec's "virtual address translation process" section.

So the fault given is the one according to shadow stack access protection (Page fault)

Anyway, you could understand this way: PMA rules must apply to the Physical address, so the translation must have been completed successfully before (pte data are virtual memory attributes)

[chara811]

Thank you, that's very clear.

[chara811]

Another question, regarding point 7 above, if pte.a=1b0 and there is an SS access fault, will the AD bit of the PTE still be updated？

[chara811]

I think that when there is a store/AMO access-fault, the page table is an erroneous page table. When encountering PTE.A = 0 or SSPUSH instruction with PTE.D = 0, hardware updates for AD should not be performed. Therefore, the priority of SS access-fault should be higher than the priority of AD updates. Is my understanding correct?

[kacouane]

Your understanding is correct

[chara811]

Ok, thank you very much.

[kacouane]

you're welcome!