riscv-software-src
Add sfence.vma in the disable_pmp function
SFENCE.VMA is illegal on implementations without S-mode. I think this should be conditionalized.
PMP changes require an SFENCE.VMA on any hart that implements page-based virtual memory, even if VM is not currently enabled. If the implementation without S-mode, does this mean that PMP registers are optional？
As you said, "any hart that implements page-based virtual memory" needs to execute SFENCE.VMA. If S-mode is not implemented, then the hart doesn't implement page-based virtual memory. So there's no contradiction here.
But I did misspeak earlier. It is true that SFENCE.VMA is illegal on implementations without S-mode. But it is also illegal on implementations with S-mode but without virtual memory. So, it needs to be conditionalized on "is S-mode implemented" and "is page-based virtual memory implemented". You can determine the latter property by checking whether satp.MODE is hardwired to 0.
But note that writing satp is illegal unless S-mode is implemented. So you should first check if S-mode is implemented, then check if satp.MODE is writable, and only then should you execute SFENCE.VMA.
As you said, "any hart that implements page-based virtual memory" needs to execute SFENCE.VMA. If S-mode is not implemented, then the hart doesn't implement page-based virtual memory. So there's no contradiction here.
But I did misspeak earlier. It is true that SFENCE.VMA is illegal on implementations without S-mode. But it is also illegal on implementations with S-mode but without virtual memory. So, it needs to be conditionalized on "is S-mode implemented" and "is page-based virtual memory implemented". You can determine the latter property by checking whether
satp.MODEis hardwired to 0.But note that writing
satpis illegal unless S-mode is implemented. So you should first check if S-mode is implemented, then check ifsatp.MODEis writable, and only then should you execute SFENCE.VMA.
Thank you for your explanation，I've introduced an implements_page_virtual_memory property for the target. But, There is a pipeline failure in Build Spike.
I think we need to do something similar to the following. Can you give it a try and see if you can make it work? https://github.com/riscv-software-src/riscv-isa-sim/pull/1584/files
I think we need to do something similar to the following. Can you give it a try and see if you can make it work? https://github.com/riscv-software-src/riscv-isa-sim/pull/1584/files
Yes, It works now.