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Published 20 hours ago • verified publisher icon riscv-software-src

illegal instruction exception

Open aakahlow opened this issue 3 years ago • 6 comments

Hi everyone,

I am having some trouble while trying to run these tests in qemu and gem5. Basically, the execution is throwing an "illegal instruction" exception when "csrs mstatus, t0" instruction is being executed in any of the tests. Binary dump does not show any problem (the machine code seems all legal and inst addresses seem aligned as well).

I wonder if anyone has any pointers on what might be wrong here? Thanks

aakahlow avatar Mar 19 '21 21:03 aakahlow

So, looking more into it, it seems like the exception is raised because we are trying to read mstatus in u-mode. Are these tests only supposed to be run on spike and do not support a linux abi? It will be great if someone can confirm this!

Thanks

aakahlow avatar Mar 22 '21 07:03 aakahlow

image While i am running the coremark benchmark as workload on gem5 I am facing this issue if any one has solution please let me know.

BSEE201905 avatar May 14 '24 14:05 BSEE201905

Yes, the generated test binaries are meant to run in M-mode. Spike can run them, but they are not at all specific to Spike.

aswaterman avatar May 14 '24 20:05 aswaterman

Is there any guide that how can i change the privilege mode form user to machine in gem5 simulator? If I can change the mode above issue can be solved?

waseem-10xe avatar May 15 '24 06:05 waseem-10xe