riscv-isac
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riscv-software-src
ISAC not calculating coverage for CSR which are getting updated only in trap handler
Dear All, I have written a basic test in which I am causing illegal instruction exception in M-mode. Here is the test. basic.txt This exception will update mcause register and will display it in the signature (which is happening correctly). I have written the following coverpoints for this test.
mcause: config: - check ISA:=regex(.*I.Zicsr.); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True mnemonics: csrrw: 0 csrrs: 0 csr_comb: mcause & 0x01 == 0x01 : 0 mcause & 0x02 == 0 x02: 0 mcause & 0x03 == 0x03 : 0
The coverpoint (mcause & 0x02 == 0x02 : 0) should have been passed due to the illegal instruction exception but ISAC is showing it in the report.
If you are using the SAIL plugin for riscof to measure coverage, the plugin only asks for coverage to be calculated between the rvtest_code_begin and rvtest_code_end labels(ref). As of now the trap handler lies outside these labels. You can edit the plugin to remove the line and you should see coverage being reported.
On another note, if the mnemonics node of the covergroup is not empty, the csr coverpoints are updated only for those instructions. But in this case, you don't need for them to be updated only when csrrw or csrrs instruction is seen. You can clear the mnemonics node and even that will allow for the coverpoints to be updated.
I think my last comment should have explained the cause. The behavior you see is by design. Hence, closing the issue. Feel free to reopen if further problems arise.