riscv-isa-sim
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Dose write-only operation to csr_seed trigger illegal instruction exception ?
https://github.com/riscv-software-src/riscv-isa-sim/blob/f7d0dba6012d49cb75b2f175a31a85cf4b2db3b3/riscv/csrs.cc#L1432
Based on spec "The seed CSR must be accessed with a read-write instruction. A read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/CSRRCI with uimm=0 will raise an illegal instruction exception. The write value (in rs1 or uimm) must be ignored by implementations. The purpose of the write is to signal polling and flushing."
It doesn't explicitly specify write-only but require read-write instructions