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Published 20 hours ago • verified publisher icon riscv-software-src

Should vector crypto instructions constraint vd_num/vs1_num/vs2_num align to lmul?

Open GuoShibo-cn opened this issue 1 year ago • 16 comments

image According to zvkned_ext_macros.h, no where constraint vd/vs1 number align to lmul. And overlap just check vs_num == vd_num. image however even with vlen =128, it would be possible to set lmul = 2, register groups could overlap with numbers not the same.

GuoShibo-cn avatar Dec 22 '23 10:12 GuoShibo-cn

Can you give a specific example of a case you think is broken today?

scottj97 avatar Dec 22 '23 17:12 scottj97

Sorry for delay. img_v3_026f_b9d5c7e7-d3df-4289-8ff2-c45445d54acg Our VLEN is 256 ,this is our simulation result, in the log we use lmul = 4, dst reg_num & src reg_num is not align to lmul, for vector arithmatic instruction this would cause illegal instruction trap, howerver spike just continue the calcualtion.

GuoShibo-cn avatar Dec 25 '23 02:12 GuoShibo-cn

cc @egouriou-rivos (and @chihminchao)

aswaterman avatar Dec 26 '23 07:12 aswaterman

Yes, the vector crypto extensions should follow the LMUL alignment requirement. Though the spec do not describe this behavior explicity, it does not make sense that register can not be the same but the content can still possible to overlap or out of the normal register range, the case v30 with LMUL=4 above.

I will create a PR for it.

timhsu404 avatar Feb 07 '24 09:02 timhsu404

what status of the PR

xinyuwang-starfive avatar Apr 28 '24 08:04 xinyuwang-starfive

cc @timhsu404

aswaterman avatar Apr 29 '24 22:04 aswaterman

@timhsu404 any progress on this issue ?

nibrunieAtSi5 avatar Jun 06 '24 23:06 nibrunieAtSi5

@timhsu404 is busy with another internal issue and may not have time on this issue this month.

chihminchao avatar Jun 07 '24 05:06 chihminchao

any progress on this issue ?

@nibrunieAtSi5 Not really. I have already done the very first version, but still tracking on some bugs. The progress is pending for now, I'll keep working on this issue after the urgent job has been done.

timhsu404 avatar Jun 07 '24 10:06 timhsu404

Vector crypto instruction VPR alignment rules: Possible alignment value: 1, 2, 4, 8 (1 for any VPR, 2 for V0, V2, ...) Prerequisite: VLEN * LMUL >= EGW

  1. Single key in .vs inst: max(EGW/VLEN, 1)
  2. Others: max(LMUL, 1)

DavidYu360 avatar Jun 08 '24 04:06 DavidYu360