riscv-isa-sim
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No csrmv instruction in the spike
8010023c: 13 05 05 4d addi a0, a0, 1232
80100240: 73 10 45 80 csrw ssp0, a0
80100244: 13 05 30 00 li a0, 3
80100248: ef f0 9f fc jal 0x80100210 <func>
8010024c: 13 04 05 00 mv s0, a0
80100250: 37 05 00 a0 lui a0, 655360
80100254: 13 05 05 00 mv a0, a0
80100258: 93 05 04 00 mv a1, s0
8010025c: ef 00 10 2c jal 0x80100d1c <printf>
80100260: 73 45 40 80 csrmv a0, ssp0
compiler gives me csrmv instruction, however spike cannot recognize it.
core 0: 0x801017d4 (0x1ac12d83) lw s11, 428(sp)
core 0: 3 0x801017d4 (0x1ac12d83) x27 0x00000000 mem 0xa002171c
core 0: 0x801017d8 (0x20010113) addi sp, sp, 512
core 0: 3 0x801017d8 (0x20010113) x2 0xa0021770
core 0: 0x801017dc (0x00008067) ret
core 0: 3 0x801017dc (0x00008067)
core 0: 0x80100260 (0x80404573) unknown
core 0: exception trap_illegal_instruction, epc 0x80100260
core 0: tval 0x80404573
core 0: >>>> trap_entry
core 0: 0x801000ec (0xef010113) addi sp, sp, -272
core 0: 3 0x801000ec (0xef010113) x2 0xa0021660
There is no standard RISC-V instruction named csrmv
. Are you perhaps using a vendor-specific compiler toolchain?