[Bug Report] When vs1 is in front of vs2, the instruction decoded by disasm is wrong.

[joii2020]

eg.

vmaccm	vm	vs2	rs1	6	vd	0x57
101101	0	11101	00011	110	01011	1010111
	0	29	3		11

vmacc.vx v11, v29, gp, v0.t vmacc.vx vd, rs1, vs2, vm

When calling disassembler_t::disassemble input: 0xb5d1e5d7 expected: vmacc.vx v11, gp, v29, v0.t results: vmacc.vx v11, v29, gp, v0.t

[scottj97]

Can you clarify what the expected behavior is vs the actual behavior?

[joii2020]

Can you clarify what the expected behavior is vs the actual behavior?

Sorry, it has now been corrected