riscv-isa-sim
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Can the offset be negative value in stride and indexed vector load store instructions?
Hi Sir, I have some vector load store page faults. For example, vluxei32.v v2, (x5), v8 vsse16.v v6, (x5), x7 When a negative integer has been moved into x7, or one element of v8, the final LSU address becomes too huge because the offset is treated as an unsigned integer.
So, the offset can not be a negative integer ???
Please give me some help. Thanks a lot!
Addresses are taken modulo 2^XLEN, so doing the calculation using unsigned arithmetic does the right thing.