what if RISC-V CPU has no member mtime_addr in aclint_mtimer_data

[profound1987]

For T-Head RSICV CPU C910, it read mtimer value via csr like following: __ASM volatile("csrr %0, 0xc01" : "=r"(result)); Actually, It has no memory map for mtimer counter value . In this case how to implement aclint function? make mtimer_time_rd32 as a weak function and re-write it in platform?

[alistair23]

If you haven't implemented the TIME CSR then OpenSBI will emulate it when the CSR access fails, have a look at sbi_emulate_csr_read()