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Published 20 hours ago • verified publisher icon risclite

Non-Debug Reset

Open enfreck opened this issue 3 weeks ago • 1 comments

I'm trying to compile this core without SRC1_DBGC_EN set. However, I get an error on line 552 of scr1_pipe_top.sv stating that rst_n is declared implicitly. Is this wire supposed to be pipe_rst_n from the module input?

enfreck avatar Feb 03 '25 19:02 enfreck