magiclantern_simplified
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Digic X: Wider address space for device IO
MMU tables from R5:
00001000-00001FFF -> 00000000-00000FFF (-1000) O:NCACH I:WB,WA P:RW
00002000-3FFFFFFF -> 00002000-3FFFFFFF ( +0) O:NCACH I:WB,WA P:RW
40000000-BEFFFFFF -> 40000000-BEFFFFFF ( +0) O:NCACH I:NCACH P:RW
BF000000-DEFFFFFF -> BF000000-DEFFFFFF ( +0) Device P:RW XN
DF000000-DFFFFFFF -> DF000000-DFFFFFFF ( +0) O:NCACH I:WB,WA P:RW
E0000000-E7FFFFFF -> E0000000-E7FFFFFF ( +0) O:WB,WA I:WB,WA P:R
E8000000-EFFFFFFF -> E8000000-EFFFFFFF ( +0) Strongly-ordered P:RW XN
F0000000-F7FFFFFF -> F0000000-F7FFFFFF ( +0) O:WB,WA I:WB,WA P:R
F8000000-FFFFFFFF -> F8000000-FFFFFFFF ( +0) Strongly-ordered P:R XN
The important bit is BF000000-DEFFFFFF -> BF000000-DEFFFFFF ( +0) Device P:RW XN
On D78 models it was RAM up to 0xD0000000.
Implications currently unknown, except maybe QEMU assumptions.