R_DTC: DTCCCR_SEC is not re-enabled for secure and flat projects

[SeanMeng0509]

Issue

The RRS bit of DTCCCR_SEC is being disabled when DTC is opened or reconfigured, resulting in some transfers taking marginally longer to complete. During operation, DTC will read transfer info blocks from a vector table defined in code into registers, update register values, and write them back to memory. When the RRS bit is enabled, the transfer is not complete, and the transfer stored in internal registers is still accurate, the DTC will skip unnecessary duplicate info block reads. This issue causes RRS to be disabled and prevents this optimization. In certain cases this results in additional clock cycles being used by DTC as it may read info blocks from SRAM multiple times when not necessary.

Workaround

No workaround is available for the releases mentioned in the applies-to-* labels.