nanorv32
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rbarzic
A small 32-bit implementation of the RISC-V architecture
U_INSTANCE/data_o_reg[0] U_INSTANCE/data_o_reg[10] U_INSTANCE/data_o_reg[11] U_INSTANCE/data_o_reg[12] U_INSTANCE/data_o_reg[13] U_INSTANCE/data_o_reg[14] U_INSTANCE/data_o_reg[15] U_INSTANCE/data_o_reg[16] U_INSTANCE/data_o_reg[17] U_INSTANCE/data_o_reg[18] U_INSTANCE/data_o_reg[19] U_INSTANCE/data_o_reg[1] U_INSTANCE/data_o_reg[20] U_INSTANCE/data_o_reg[21] U_INSTANCE/data_o_reg[22] U_INSTANCE/data_o_reg[23] U_INSTANCE/data_o_reg[24] U_INSTANCE/data_o_reg[25] U_INSTANCE/data_o_reg[26] U_INSTANCE/data_o_reg[27] U_INSTANCE/data_o_reg[28] U_INSTANCE/data_o_reg[29] U_INSTANCE/data_o_reg[2] U_INSTANCE/data_o_reg[30] U_INSTANCE/data_o_reg[31] U_INSTANCE/data_o_reg[3] U_INSTANCE/data_o_reg[4] U_INSTANCE/data_o_reg[5] U_INSTANCE/data_o_reg[6] U_INSTANCE/data_o_reg[7]...
see https://sourceforge.net/p/iverilog/mailman/message/28324461/
htransd and htransi are 1-bit outputs from nanorv32_pil. In AHB they are a 2-bit signal. NON-SEQ transfers are signalled by driving htrans to 2'b10.
Currently mul/div instructions are declared in the rv32i section for convenience because the generator only picks rv32i
It looks like that the tdo_padoe_o signal is asserted too late at the begining of the shift_dr state. Looks like it is not captured by the tests in adv_debug_sys because...
Currently -march=RV32IM is used by default
Current, the signal is not sticky and may not be captured by the testbench
To allow C-only startup code - load SP from codemem[0] - branch to codemem[4]