PLL REFDIV values > 1 considered by vcocalc.py (#951)

[alastairpatrick]

Prior to this change, the vcocalc.py script only considered PLL configurations with REFDIV = 1. Sometimes it is beneficial to use PLL configurations with REFDIV > 1.

The new version of the script considers all REFDIVs that would yield a valid reference frequency, that is, a reference frequency >=5MHz. So for a 12MHz crystal, valid REFDIVs are 1 and 2.

I added a --ref-min option, consistent with --vco-min and--vco-max, allowing a more conservative minimum reference frequency, such as 6MHz to be specified.

REFDIVs are considered in ascending order so that, if the best match is achievable using multiple REFDIVs, the lowest REFDIV is selected. This is motivated by the set_sys_clock_pll() SDK function, which only supports REFDIV = 1.

Examples of new script output:

; 133MHz is achievable with REFDIV of 1 or 2 but 1 preferred by script
>python vcocalc.py 133
Requested: 133.0 MHz
Achieved: 133.0 MHz
REFDIV: 1
FBDIV: 133 (VCO = 1596.0 MHz)
PD1: 6
PD2: 2

; 12.288MHz is a good crystal for audio applications but 48MHz USB clock is only achievable with REFDIV = 2
>python vcocalc.py --input 12.288 48
Requested: 48.0 MHz
Achieved: 48.0 MHz
REFDIV: 2
FBDIV: 125 (VCO = 768.0 MHz)
PD1: 4
PD2: 4

; Clocks suitable for 44.1kHz audio applications with 12MHz crystal are easier with REFDIV = 2
>python vcocalc.py 88.2
Requested: 88.2 MHz
Achieved: 88.2 MHz
REFDIV: 2
FBDIV: 147 (VCO = 882.0 MHz)
PD1: 5
PD2: 2

[lurch]

Links to #951