RP2040 XOSC_CTRL FREQ_RANGE doesn't match documentation

[ionspin]

Hi,

I'm new to embedded programming, so I might be doing something wrong, but to me it seems that XOSC_CTRL FREQ_RANGE is set to 0xFA5 when booting pico instead of 0XAA0 as the documentation states (2.16.7. XOSC CTRL):

Frequency range. This resets to 0xAA0 and cannot be
changed.
0xaa0 → 1_15MHZ

Note that I am not using Pico SDK

Here are my logs when pico boots directly after power cycle:

XOSC CTRL before enabling hal.oscillators.CTRL__struct_1948{ .FREQ_RANGE = 4005, .ENABLE = 3358, ._NU = 0 } 

4005 is 0xFA5 and 3358 is 0xDIE, while I would expect FREQ_RANGE to be 2720 (0XAA0)

Furthermore if I enable external oscillator by writing 0xFA5 and reading the register

XOSC CTRL after write hal.oscillators.CTRL{ .FREQ_RANGE = 4005, .ENABLE = 4011, ._NU = 0 }

the XOSC STATUS register doesn't complain

XOSC stable! hal.oscillators.STATUS{ .FREQ_RANGE = 1, ._NU = 0, .ENABLED = 1, ._NU2 = 0, .BADWRITE = 0, ._NU3 = 0, .STABLE = 1 }

however if I write the expected 2720 (0xAA0) this is the result

XOSC CTRL after write hal.oscillators.CTRL{ .FREQ_RANGE = 2720, .ENABLE = 4011, ._NU = 0 }
XOSC stable! hal.oscillators.STATUS{ .FREQ_RANGE = 1, ._NU = 0, .ENABLED = 1, ._NU2 = 0, .BADWRITE = 1, ._NU3 = 0, .STABLE = 1 }

Indicating BADWRITE when using AA0

I've rechecked this by running blink.uf2 sample and reading the 0x40024004 address and it seems that BADWRITE is also 1 there because the CTRL register is set to AA0

(gdb) x/x 0x40024000
0x40024000:     0x00fabaa0
(gdb) x/x 0x40024004
0x40024004:     0x81001001
(gdb) x/t 0x40024004
0x40024004:     10000001000000000001000000000001     

 1000 0001 0000 0000 0001 0000 0000 0001
|S-------B--------------E-------------FF|

Here is the SDK code Blink example should be using to initalize XOSC :

#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ    _u(0xaa0)
...
void xosc_init(void) {
    // Assumes 1-15 MHz input, checked above.
    xosc_hw->ctrl = XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ;

    // Set xosc startup delay
    xosc_hw->startup = STARTUP_DELAY;

    // Set the enable bit now that we have set freq range and startup delay
    hw_set_bits(&xosc_hw->ctrl, XOSC_CTRL_ENABLE_VALUE_ENABLE << XOSC_CTRL_ENABLE_LSB);

    // Wait for XOSC to be stable
    while(!(xosc_hw->status & XOSC_STATUS_STABLE_BITS));
}

Could this be similar to errata RP2040-E10 regarding ROSC status register and BADWRITE?

[aallan]

Ping @Wren6991

[nathan-contino]

necro-ping @Wren6991