USB Host Controller documentation

[alimansfield2016]

There are a couple issues I think I've found with the HCD documentation, and a couple of queries regarding the behavior of the PHY.

Firstly, in section 4.1.2.7.2. HOST CONTROLLER - IN, for the control phase, EPx control register is specified at location 0x80, whereas in Table 404 - DPSRAM Layout, this register is placed at 0x100. Again similarly EPx buffer control register is given to be at 0x100, where it should be 0x80.

Secondly, there seems to be no information on the behavior of the Host In Data phase if the device NAKs instead of returning data. How is this handled by the hardware?

Thirdly, in Table 404 there are the "Spare" registers. In Host mode, are these completely ignored by the controller? Or could they be used similarly to the Interrupt IN endpoints, but rather as OUT endpoints.

Finally, on a similar note to my third point, Can the "Interrupt" endpoints be used for non-interrupt transfers? If so what is the behavior of this if multiple are enabled/active simultaneously?