SPI slave DMA fill of TXFIFO triggered too soon.

[djfarrell]

I am trying to keep the TX DMA ready for a SPI slave transfer so when a read occurs, simultaneous TX data is available. This works fine on the first transfer but for a continuous transfer (using an _isr to re-load the DMA source address) the TXFIFO is populated with old data before the new source memory address is set. Only workaround I have found is to lead with 8 bytes (FIFO size) of fill in my message to get remainder of messages through. Any way to clear the TXFIFO or keep the DMA from filling it? Other than this the process is reliable at 15MHz. Also, the ring does not seem to do anything from my tests in slave mode.