Cannot connect to STM32G431
The debugprobe can connect to most devices I have, except for the STM32G431. I can use other probes (original and clone j-links) to connect to the same target, using the same host software (namely, probe-rs, but that shouldn't matter much).
The host software issues a line reset, followed by a JTAG -> SWD switch sequence, followed by another line reset, 3 idle bits, and a DPIDR read. I have made the following logic analyzer captures (only for the DPIDR read to fit the screenshots) to illustrate my problem:
STM32G4 with debugprobe, notice the missing ACK bits:
STM32G4 with J-Link (in CMSIS-DAP configuration, with WinUSB driver) - note that SWDIO starts high after line reset, but clock polarity is the same:
STM32G4 with a clone j-link, notice the seemingly flipped clock polarity (although data changes just before SWCLK rising edge):
STM32F0 with debugprobe:
While this issue looks to be STM32G431 specific, I wonder if the debugprobe firmware could be adjusted for better compatibility, e.g. by delaying the clock output just slightly?
If you can point to a specified minimum/maximum setup/hold time that a SWD probe should respect and debugprobe violates, I will investigate.
To the best of my knowledge, debugprobe conforms to what ARM prescribes - the issue seems to be that this particular target doesn't.
Data correctly changes on the falling edge and is stable on the rising edge of SWCLK. That MCU implementation is probably bugged and samples on the wrong edge.
Does adding a series resistor (100R) to either SWCLK or SWDIO make the target respond?
Indeed it seems that 100R on SWCLK makes the target behave. The problem is, I removed the resistor and the target keeps working as expected :/