Rachit Nigam

[fud] State/stage conflation confuses implied state detection

1

`fud` has the ability to automatically detect the name of the input and output *state* based on the suffix of the file. For example: ``` fud e in.futil -o out.sv...

Parallel assignment asserts do not work with icarus verilog

2

https://github.com/cucapra/calyx/pull/847 attempted to enable parallel assignment checking with the icarus backend but inadvertently made all tests fail (another argument for #755). The problem is that the `onehot` primitive returns false...

I wasn't sure if it does but don't want to investigate it right now.

Parameterize systolic generator to use different PE

1

Add an option to the systolic array generator to use a specific `mac_pe` implementation. This will allow us to, say, replace the default `mac_pe` implementation which uses sequential multipliers with...

`tdcc`: Incorrect FSM generated in presence of `par`

4

The following program incorrectly computes the final value in `y_int0` to be `0`. The expected value is `1`: ``` import "primitives/core.futil"; component main(@go go: 1, @clk clk: 1, @reset reset:...

The original implementation of `fud` conflates notions of "state" and "stages". States are file system states that can be transformed by stages. The conflation occurred because most of the time,...

Unstable reads

1

A pass that marks ports as stable or unstable depending on where they receive values from. If the value comes from a continuous assignment rooted in stateful elements, the read...

`resource-sharing`: Sharing generates invalid verilog

5

The [unrolled MVT](https://github.com/cucapra/calyx-evaluation/blob/master/benchmarks/unrolled/linear-algebra-mvt.skip) benchmarks generates invalid verilog: ``` %Warning-UNOPTFLAT: /var/folders/sk/f158_qn147vc0jhjsfdcswq40000gn/T/tmpweji9c61:1076:18: Signal unoptimizable: Feedback to clock or circular logic: 'main.add9_right' 1076 | logic [31:0] add9_right; | ^~~~~~~~~~ ... Use "/* verilator...

Bitwidth Reduction

1

Several cells in the library have input and output bitwidths. A bitwidth reduction pass analyzes the uses of output ports and, based on the use, changes the input bitwidths. For...

creduce for Calyx

5

I was debugging #329 and wrote down a simple script for differential testing. Then, I slowly reduced the program to find a minimal program. A few problems that need to...