stabilizer
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quartiq
Firmware and software for the Sinara Stabilizer module with high speed, low latency ADC/DAC data processing and powerful DSP algorithms in between
This Issue serves as an overview over the current driver software development status. ## High importance ### Drivers - [x] DAC11001A Driver DAC driver - [x] I2C Relay control shift...
## Description This PR implements control of devices on Pounder through MQTT. These parameters are configurable through MQTT (topic prefix: `/settings/pdh/ch/`). ```rust pub struct PDHChannel { pub osc_frequency: f32, //...
When specifying a static IP address in the firmware build command but having a incorrect broker address at the same time, the program panics at `assertion failed: protocol_addr.is_unicast()`. If both...
### Motivation In one of our [Stabilizers](https://github.com/OxfordIonTrapGroup/stabilizer/tree/l674-rerewrite) we needed a custom request-response topic for on-demand read access to a value (in this case the output of a filter). ### Limitation...
Bumps [enum-iterator](https://github.com/stephaneyfx/enum-iterator) from 1.1.3 to 1.2.0. Commits e783403 Bump versions 3adab1c Improve enum traversal c79d71b Implement Sequence for arrays See full diff in compare view [](https://docs.github.com/en/github/managing-security-vulnerabilities/about-dependabot-security-updates#about-compatibility-scores) Dependabot will...
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Some notes: - For asynchronous updates, the LDAC pin is not required, and must be connected to 0 V permanently.
https://github.com/quartiq/stabilizer/pull/590#pullrequestreview-1066610618 We should try to get away from `DelayUs`/`DelayMs` at some point in the future. The API is an invitation for error: `Into` strips units, granularity, and context as `delay_us(something.into())`...
Because the RTIC Monotonic Frequency is the maximum frequency at which RTIC tasks can be scheduled this currently limits the sample rate for the Driver header ADC since it is...
Delays (typ, max in ns) in the SPI path: - MAX9130: 1.8, 3.0 - DS90CV: 1.1, 1.5 - LTC2320: na, 5.5 - This is more difficult to say from the...
Analyze the timing requirements when using the DMA sample acquisition architecture for ADC/DAC operations for low batch sizes (e.g. 1 or 2). If possible, we may want to eliminate the...
