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FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.

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I have created a new interface. During the adaptation, I found that the erasing action was particularly fast, but in fact, the erasing was not successful, and the flash returned...

Dear all, what would be needed to add support for Xilinx Virtex 6 series of FPGAs? I guess the reason that there is no support so far is mainly due...

Had to spend some time debugging the thing, moved some logic to sync domain and added a 1 clock cycle wait at the end of the transaction. Also, cleaned up...

I wonder if I can complete the support of xc7z035 only by adding it in the format of other FPGA models in the xilinx_bscan_spi.py?