Spatial layout for qualtran circuits

[zphy]

Given an abstract circuit, is there a convenient way to use qualtran to compile all the way down to a physical spatial layout of the circuits, as is done in Gidney-Ekera's factoring paper? If not, what would be the recommendation to build on top of qualtran to achieve this, assuming that one already knows the layout but wants to use qualtran to express it? An example could be the Gidney factoring layout, or the known layouts in a magic state factory.

[mpharrigan]

Thanks for the question! The data structures in qualtran were tailored for expressing logical operations at increasing levels of abstraction. The idea is: you'd express your algorithm using Bloqs which can be compiled down to a logical gateset (like clifford+T+Toffoli) and then you'd use something else to lay it out. Right now, we have qualtran.surface_code which will give you the physical costs (qubits, wallclock time) using some models from the literature but it doesn't explicitly lay anything out.

You'd likely need a different set of data structures to represent the constraints / reality of your hardware architecture. For a surface code, something like Cirq with its cirq.GridQubit is probably close to what you'd want to express the physical layout. Automating & optimizing the layout is a very challenging problem. This project aims to do this: https://github.com/latticesurgery-com/lattice-surgery-compiler. Interoperability with qualtran would be a great feature but it doesn't exist yet #447.

The Gidney-Ekera factoring layout (as I understand it) was done by hand in sketchup, which is a generic 3d modeling program.