qiskit-hackathon-korea-22
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qiskit-community
Project B : Metal - Designing a qubit chip
Abstract
The designing of a four qubit system using Qiskit Metal.
Description
Using Qiskit Metal, design a single plane, four-qubit chip using superconducting qubits, which are coupled together in a ring pattern (qubits connected to nearest two neighbours) with coplanar waveguide (CPW) bus resonators, with each qubit having a CPW readout resonator. The readout resonators should be coupled to transmission line(s) which connect to launcher pad(s) for wire bonds.
The qubits can be newly written qcomponents, as can the capacitive couplers.
The project members are to determine the actual physical layout, with the below target parameters in mind. In addition, the design should take into consideration the following available electronics.
• Available microwave sources: 5.25 - 5.75 GHz, 7.0 – 10.0 GHz • Amplifier bandwidth: 6.75 – 7.75 GHz
| Parameters | Target Value | Parameters | Target Value |
|---|---|---|---|
| Anharmonicity (Ec) | 300 MHz | χ | 400 kHz |
| g_bus | ~60 MHz | Q_ext | 20,000 |
Be mindful of potential cross talk issues between busses when deciding frequencies for your busses, and choose your qubit and readout frequencies with your electronics in mind.
The project members can also decide on the chip size, though should consider issues such as, potential box/substrate modes, or cross talk between the different components on the chip. It can be assumed wirebonds are available to be added where desired.
If new qubit qcomponents are created for this project, some modification to analysis code may also be required (eg. LOM analysis code currently presumes floating transmons, but can function with grounded transmons with minor modifications).
Bonus Challenge
Attempt a time evolution simulation of a portion of your chip using the LOMtoSeqMapper class.
Members
No limit. Will be Invited to the dedicated channel and a guide will be given there.
- @githubhandle
- @githubhandle - Slack:
@slackhandleemail:[email protected] - Qiskit Coach: @githubhandle
Deliverable
• The design notebook. • Documentation showing the successful simulation/analysis of the chip design meeting the desired parameters. Explanations on design choices should also be included where appropriate. • A gds file of said design.
