riscv-dbg
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JTAG_TAP status can't be exited shift_ir, and traped in loop
// Set IR, but only if it needs to be set.
task set_ir(input logic [IrLength-1:0] opcode);
logic opcode_unpacked [IrLength];
// check whether IR is already set to the right value
if (this.ir_select == opcode) return;
{<<{opcode_unpacked}} = opcode;
write_tms(1); // select DR scan
write_tms(1); // select IR scan
write_tms(0); // capture IR
write_tms(0); // shift IR
write_bits(opcode_unpacked, 1);
write_tms(1); // update IR
write_tms(0); // run test idle
this.ir_select = opcode;
endtask
// Assumes JTAG FSM is already in shift DR state
task readwrite_bits(output logic rdata [$], input logic wdata [$], input logic tms_last);
for (int i = 0; i < wdata.size(); i++) begin
jtag.tdi <= #TA wdata[i];
if (i == (wdata.size() - 1)) jtag.tms <= #TA tms_last; // tms_last ? exit1 DR : shift DR
cycle_start();
rdata[i] = jtag.tdo;
cycle_end();
end
jtag.tms <= #TA 0; // tms_last ? pause DR : shift DR
endtask
if execute jtag.tms <= #TA 0; // tms_last ? pause DR : shift DR
, jtag_tap status changed to pause-ir, exit-2-ir, shift-ir, can't back to idle