target: Add Verilator 5 support

[paulsc96]

Requirements for using Verilator 5 with our testbench (sorted by difficulty):

• [x] Get, use new release of common_cells incorporating https://github.com/pulp-platform/common_cells/commit/8ac55cf0933e8350a570ea3f3b975667342d60be
• [x] Merge and use https://github.com/pulp-platform/axi_llc/pull/18
• [x] Get axi_sim_mem and its dependencies included without including incompatible simulation/test code.
• [x] ~~Fix, Merge, and use https://github.com/pulp-platform/riscv-dbg/pull/167~~ Just include jtag_test_simple
• [x] Work around sim/src/vip_cheshire_soc.sv:90: Unsupported: DPI argument of type DYNARRAYDTYPE on buffer[]: Labelled Wontfix, so use chunked transfers like Croc did.
• [x] Work around strange compile issue with UART readout (to be investigated).
• [ ] Make binary reading workaround a bit less terrible
• [ ] Reduce verilator runtime further, investigate GCC vs clang
• [ ] Try to add back as much functionality as we can, stub the rest well
• [ ] Work around or exclude unsupported AXI drivers for serial link
• [ ] Work around or exclude unsupported device models (only SPI model?)

Fixes #180 and Closes #39 (outdated).

@thommythomaso @phsauter