axi_mem_if
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allow respond to read transactions between address write and data write to speed up response
Current implementation goes to wait valid state after receiving an address write, until the data write comes The proposal is to permit to respond to read requests that may come in between to speed up the response time
This is useful for example when integrating a DMA
We have tested this change with the CVA6 smoke tests and benchmarks, apart from our own integration tests with other peripherals such as DMA.