AXI4+ATOP on chip memory slave

[WRoenninger]

This adds two modules:

• axi_to_mem: Salve module, max throughout simultaneous read/writes 50%, read or write 100%.
• axi_to_mem_banked: With enough banks 100% throughput with simultaneous reads/writes.

Notes to Bender: For the dependencies pulp-platform/tech_cells_generic has been directly added. In there the tc_sram module is used for the testbench to serve a memory model. -> For all conflicts in the dependency tree of Bender, the versions specified by the Bender.yml of this repo has to be used.

Edit: Now bender.lock is also checked in so CI should pass now

This depends on changes form #116.

[WRoenninger]

The conflict in the Bender dependencies, leads to the failure of the ci.

[WRoenninger]

Rebased onto current master.

[WRoenninger]

Timeout for the complete CI seems no longer to be sufficient enough long when adding axi_to_mem_banked to ci.

[WRoenninger]

Rebased onto current master for ci fix by #129.

Ci will time-out as testing for axi_to_mem with the full parameterizations runs for multiple hours.

[stevobailey]

Bump

[micprog]

Merged with #244 and #248