Memory Alignment Limitation in Ara

[mrbilandi]

Hello,

I am using SYCL for vectorization. I implemented a simple vector addition (c = a + b, where a, b, and c are double arrays like double a[4096]) as a SYCL kernel and offloaded its operation to Ara. The VLEN is set to 2048, and NrLane is 2. The problem I have is that when I set the array size to something other than a multiple of VLEN (for example, double a[4033]), I encounter an exception when running the vector addition. However, when I set the array size to 4096 (double a[4096]), it offloads and runs successfully on Ara.

To compare the results, I conducted the same tests on another RVV we have on a laptop with a RISC-V processor that supports RVV 1.0, and I didn’t see any exceptions occurring when I ran the vector addition operation with different array sizes.

It seems that there is a memory alignment limitation in Ara that should be taken into account when writing the application.

Is there any memory alignment limitation when working with Ara? Should we be able to offload arrays of any size to Ara?

Thanks

[mp-17]

Hello @mrbilandi,

Interesting! There should be no such limitation. Are you on FPGA with OS or bare-metal? Do you have a simple toy example so that I can reproduce it?

[mrbilandi]

Hi Matteo,

Thanks for your response. I am on FPGA with OS and running the code in a server-client mode, where the client sends RVV instructions and data to a server running on CVA6, which then executes the instructions.

I have integrated Ethernet into the ARA-CVA6 OS, as we discussed earlier. I will upload the code to our repository soon for your reference.

But at the moment, I don’t have a simple code that can run directly. it requires the server to be running.