Results 78 issues of Jacob Lifshay

[Yosys](http://www.clifford.at/yosys/) is currently the de-facto standard implementation for open-source synthesis (we're currently using it along with [nmigen](https://github.com/nmigen/nmigen) to build a [completely open-source Power/RISC-V SoC with CPU/GPU/VPU](https://libre-soc.org)). Add support for converting...

C-enhancement
T-llhd-conv

Add support for generating FSMs from behavioral code. According to the paper, the lowering pass currently fails when encountering behavioral code with more than a initialization and a single infinite-loop...

A-opt
C-enhancement

When placing more than 24 elevators in a single X,Z column, the unconfigured elevators can't be removed since the UI only has the remove button on configured elevators. This happens...

### Feature description it would be useful to allow opening additional terminals since many phones have enough ram that opening lots of terminals isn't an issue ### Additional information constant...

https://rust-lang.zulipchat.com/#narrow/stream/257879-project-portable-simd/topic/splat.20no.20longer.20compiles.20for.20release.20builds/near/352702343 @bjorn3

for toml==0.10.2: ```python3 import toml toml.loads('a={b=2024-01-01 }') ``` incorrectly produces the following error: ``` Traceback (most recent call last): File "/lib/python3.7/site-packages/toml/decoder.py", line 512, in loads multibackslash) File "/lib/python3.7/site-packages/toml/decoder.py", line 778,...

https://doc.rust-lang.org/std/thread/fn.scope.html

2024

imho it'd be useful for code to be able to be generic over mutability. related: https://github.com/rust-lang/rfcs/issues/414

One of the other SIMD instruction sets that you may want to consider is RISC-V's vector extension, because it takes a totally different approach than most other common ISAs: it...

on 32-bit platforms, long/unsigned long are 32-bits, the long long variants have to be used for 32-bit platforms. https://github.com/swgillespie/gccjit.rs/blob/314741b4311d465ab79e6640413b9892e21f413f/src/types.rs#L93-L94