raplcap
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20 hours ago •
powercap
powercap
RAPL power capping C interface with multiple implementations
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The April 2021 Intel Software Developer's Manual Volume 4 adds Table 2-47 in Section 2.17.6 with new information on the `MSR_DRAM_POWER_LIMIT` register for Ice Lake Xeon CPUs (0x6A and 0x6C)....
This issue is filed mostly to document the idea, although it is unlikely to be implemented. Currently there is only one way to set a power value to 0, however...
enhancement
wontfix