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Sunflower Full-System Hardware Emulator and Physical System Simulator for Sensor-Driven Systems. Built-in architecture modeling of Hitachi SH (j-core), RISC-V, and more.

Results 83 sunflower-embedded-system-emulator issues
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Implement CSRs for RISC-V.

Enhancement

The RISC-V implementation files in 'sim/' have inaccurate copyright date (should be `2017-2018, Zhengyang Gu (author)`) and several are missing the copyright header / block. (cc: @Z-Gu)

Verify

RISC-V implementation source mixes tabs with spaces (or uses spaces instead of tabs) in several files: - `decode-riscv.c` - `decode-riscv.h` - `instr-riscv.h` - `machine-riscv.c` - `opstr-riscv.h` (stray space right after...

Verify

Via @Z-Gu: Sunflower SegFaults if the first thing I enter in sf terminal is ctrl+D (^D,EOF)

Verify

Ran make in sim and got the following error: gcc -g -DSF_L_ENDIAN -Wall -g -m32 -O0 -c randgen.c In file included from /usr/include/features.h:447:0, from /usr/include/bits/libc-header-start.h:33, from /usr/include/math.h:27, from randgen.c:38: /usr/include/gnu/stubs.h:7:11:...

Verify

Please see Jan's description of the error at issue #108 . From my own experience (on Linux), building the riscv cross-compiler multiple times from a clean pull has resulted in...

Bug

If given an exceedingly large memory size, the `uncertain_sizemem()` function will return an error stating "`Cannot compute required number of covariances without overflow`". According to the code in `uncertain_sizemem()`, found...

Enhancement