llvm

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It is currently impossible to assemble arithmetic/logic instructions with immediate operands larger than 31.

phire

``` phire@nirrit:~/projects/llvm/build$ echo "st r0, (r3+sp)" | bin/llvm-mc -arch=videocore -show-encoding .text llvm-mc: /home/phire/projects/llvm/llvm32/lib/Target/Videocore/MCTargetDesc/VideocoreMCCodeEmitter.cpp:134: unsigned int {anonymous}::VideocoreMCCodeEmitter::getMachineOpValue(const llvm::MCInst&, const llvm::MCOperand&, llvm::SmallVectorImpl&) const: Assertion `Kind == MCExpr::SymbolRef' failed. 0 llvm-mc 0x000000000060c21d 1...

phire

phire

Operands don't show scalar register offsets and will potentially show the wrong orientation.

phire

It might be possible to remove duplication in the instruction formats and multiclasses by using multiple inheritance.

phire

Should softfail instead.

phire

Need to add checking for valid registers when adding a memoperand.

phire

phire

phire

phire