Petr Penzin

> Arm has already announced processor cores with SVE support that cover almost the full range of the A architecture profile; the latest [announcement](https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/first-armv9-cpu-cores) was 3 weeks ago and concerned...

Oops, closed by accident.

> So I can't see how introducing masked memory operations into wasm is currently viable, when they're not supported well (or at all) on the majority of currently available hardware....

Matching AVX-VNNI most likely would not be feasible for this proposal, unless it can be efficiently emulated in SSE - there is no intended AVX support here at all. There...

We should probably look into expected instruction sequences within ISA limits that the proposal has, though I can't promise it is going to make into MVP.

I've filed WebAssembly/flexible-vectors#15 for this a while back, though given what is flexible vectors about it would need to be consistent across platforms to be part of it.

@zeux, thank you for the input! > allows changing vector lengths (to a value smaller than the maximum) It hasn't been officially prohibited yet, but it is considered problematic -...

> If SIMD were to be used, this buffer must be a multiple of the SIMD width. When SIMD width is dynamic and unbounded, this makes it impossible to use...

The idea is that operations in this proposal corresponds to a non-repeating sequence of native ops, so the maximum vector length should be same as hardware register size. With this...

Sorry for taking this long to response :) Completely agree with your suggestions, I should have probably added that to the presentation. Trying to schedule a slot to present this...