Pascal Cotret

I'm still unsure about the best solution to solve this issue... - Installed the `riscv-gnu-toolchain` in `/opt/riscv` - Added `/opt/riscv/bin` folder to my `PATH` - Compiled Spike with `prefix=/opt/riscv/` `pk`...

I know @duskmoon314 PR is nearly 2 yo. However, I'm still facing the issue described in #140 and this PR doesn't solve it in my case. Anyone facing this recently?

Well, as I've worked on the 41P, this should not be an issue. I'll try it this weekend.

Hi @nuntipat, happy to find something who had time to work on it finally!

I had a look back in [my notes](http://pcotret.gitlab.io/blog/processor_in_litex/#interrupt-controller) and the [MIE register documentation](https://docs.openhwgroup.org/projects/cv32e41p-user-manual/control_status_registers.html#machine-interrupt-enable-register-mie). `0x7FFF0880` is written in the MIE register.  # In the old Antmicro fork https://github.com/antmicro/cv32e40p/blob/master/rtl/riscv_cs_registers.sv#L619 ```verilog mie_n.irq_fast...

Hi @nuntipat @enjoy-digital, as far as I understand, support for the OpenHwGroup 40P has been done. @nuntipat also pushed a modification for the URL in https://github.com/litex-hub/pythondata-auto/commit/a9ff1bd3ef9fc21ec7661a36b24a963533394197 Is there another PR...

> This behavior is more or less common to all distro since few month. One solution is to add `--break-system-packages` after `pip install` Another solution is to create a file...

Got a similar issue, I had to `sudo ` in order to make it run :neutral_face:

Came back to this issue as I was interested in other OpenHwGroup cores. There are several errors related to a `uvm_error` directive during Verilator model compilation. For instance : ```bash...

https://github.com/openhwgroup/core-v-verif/issues/2362 A few weeks ago, I was blocked while trying to emulate the CV32E40S with their `core-v-verif` verification environment. I assume there's still some work to make it run with...