patgro1
patgro1
```vhdl library ieee; use ieee.std_logic_1164.all; library my_lib; use my_lib.module_a_pkg.all; use my_lib.module_b_pkg.all; -- Xilinx components library unisim; entity top is port ( clk_i: in std_logic; rst_i: in std_logic; data_i: in std_logic_vector(31...
> The unisim library and vcomponents is acually part of the xilinx install and can just be added to the project. So the example does not really mandate this feature....
Awesome! Thanks! I’ll do that throughout the week.
Same as #118 ??